The Chipus DDR PHY is designed to support LPDDR4, LPDDR4x and LPDDR5 SDRAM.

This allows the host SoC to easily be configured for the specific DDR SDRAM variant used in the system via simple software control, allowing one chip to target multiple applications using different DDR types.

The Chipus DDR PHY has been optimized to take advantage of the memory configurations and packaging to reduce the total memory subsystem power and area.

The DDR PHY is designed to comply with DFI 5.1 memory standard so the PHY can work seamlessly with DDR Memory controllers from any supplier that compliant with the DFI 5.1 Standard.